| 摘要 |
An apparatus, system, and method for speeding up data transfers while reducing bus contention during repeated consecutive read-write operations. By reducing the length of time during which selected data pulses are driven on the memory bus, a higher percentage of usage of the memory bus may be attained without increasing the likelihood of bus contention and resulting degradation or damage to the memory system. The selected data pulse is preferably the write data pulse driven on the memory bus by the memory controller. A zero bus turnaround protocol may be implemented. The memory controller may include interface circuitry and write control circuitry that outputs an associated control signal to a three-state buffer. The three-state buffer, after being enabled by the associated control signal, drives write data on a data line of a memory bus. The turn-on delay associated with the three-state buffer exceeds the turn-off delay also associated with the three-state buffer. Thus, the three-state buffer drives data pulses on the data line for a shorter period of time than the period of time that the associated control signal is provided by the write control circuitry to enable the three-state buffer. The write control circuitry may output a shortened associated control signal. The associated control signal may be asserted for a shorter period than the memory controller clock period or the duration of a memory read data pulse. The write control circuitry may implement a turn-on delay or a shortened control signal which ends prior to the end of the memory controller clock pulse.
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