| 摘要 |
PURPOSE: An arbitration apparatus of a dual port SRAM is provided to solve a bus contention without spending unnecessary time and using a flag. CONSTITUTION: The apparatus includes a host(20), a control signal generation part(22), a DPSRAM(24) and a DSP(26). The DPSRAM comprises two ports for data write/read, and writes/reads the first data(DATA1) by interfacing with the host through the first port, or writes/reads the second data(DATA2) by interfacing with the DSP(26) through the second port. The host is a terminal apparatus using the first port, and generates the first clock signal(CLK1) and the first port access control signal(CSN1) synchronized to the first clock. The control signal generation part(22) receives the first clock signal and the first port access control signal from the host(20), and applies a port access control signal(CSN1_N) synchronized to the second clock signal to the first port of the DPSRAM(24), and also applies a clock signal(CLK1_N) to the first port. The DSP(26) uses the second port of the DPSRAM(24), and generates the second clock signal and the second port access control signal(CSN2) synchronized to the second clock signal.
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