| 摘要 |
PROBLEM TO BE SOLVED: To provide a control circuit for validly utilizing the capabilities of a CPU by reducing the waiting time of the CPU. SOLUTION: This control circuit is provided with a circuit for decoding instructions from a CPU, a circuit for deciding whether the decoded instructions can be simultaneously processed, and a buffer for temporarily storing the instructions and data. For the instructions which can be simultaneously processed, the instruction is received, and then the next instruction is received without waiting for the completion of the instruction, so that the plural instructions can be processed simultaneously.
|
