| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device allowing a memory test to be performed efficiently in a short time even when I/Os exceeding in quantity, the hardware limit of a tester are provided. SOLUTION: When the memory test of a DRAM macro 2 is performed, a macro selection signal MSL is input into a decode circuit DC2 for decoding. Based on the signal, a selector circuit ST outputs the signals output from the selector circuits S1 to S12 of the DRAM macro 2. In a light cycle, a decode circuit DC1 decodes six patterns of I/O selection signals SEL. Based on the decode signals, the selector circuits S1 to S12 output selectively the data output from the DRAM macro 2. Thus, the test data of 72-bit input into the selector circuits S1 to S12 is output in order from the selector circuit ST every 12 bits in taking 6 cycles.
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