| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory data transmission method and a memory data transmission system with a high data transfer efficiency that can realize data transfer without setting of an active command, setting of a row address, and a delay due to CAS latency in the case that data are transferred between two memories consisting of synchronous DRAMs. SOLUTION: In the case of outputting a 2nd synchronous DRAM packet stream from a 1st synchronous DRAM, the 1st synchronous DRAM outputs a data enable signal synchronously with the packet stream. The 2nd SDRAM is in a standby state while setting row and column addresses to the 2nd synchronous DRAM before data are transferred and provides an output of a ready signal. In the case of outputting a packet stream from the 1st synchronous DRAM, when the 2nd synchronous DRAM is not in ready, the row and column addresses of the 1st synchronous DRAM are returned to addresses where a transmission error takes place and the data are retransmitted.
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