| 摘要 |
PROBLEM TO BE SOLVED: To shorten the processing time of a connection tracking method in the layout verification of a semiconductor integrated circuit and to reduce its memory capacity. SOLUTION: This method inputs a file in which the rules of the layout verification area described (101), inputs graphic data undergoing layout (102), extracts the diagram of the wiring layer of an integrated circuit and of a diffusion layer with a graphic operation (103), performs the arrangement processing of connection rules (201), reads one connection tracking rule by reading connection tracking rules (104), detects the place where graphics are overlapped on the basis of the read connection tracking rule (105), performs graphic connection tracking making the potentials of the graphics the same (106), discriminates whether the connection tracking rule is short-circuited (108), reports a short- circuited place, if any (109), returns to the connection tracking rule reading processing if there is a residual of the connection tracking rule (202) and sequentially performs connection tracking processing in the layout verification processing by finishing the processing if there is no residual.
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