| 摘要 |
PROBLEM TO BE SOLVED: To shorten the access time even when the address of the read destination is frequently changed. SOLUTION: When valid data for four addresses are read from an SDRAM 32 by a burst transfer, only the valid data of a requested address are outputted to a CPU 12. On the other hand, valid data for remaining for three addresses are stored in a cache 24 by a cache control circuit 20. When an address included in the next read request is matched with the address of the read source of valid data stored in the cache 24, the SDRAM 32 is not accessed and the valid data stored in the cache 24 are outputted to the CPU 12.
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