发明名称 Frequency synthesizer with phase locked loop (PLL) with two frequency dividers
摘要 A phase locked loop frequency synthesizer includes a cascade of phase comparator, loop filter and frequency generator sequences 21, 22, 23 and 21', 22', 23' with respective feedback frequency dividers 24'. The division ratio of at least one of the dividers is modulated by a controller 26 to provide fractional division values.
申请公布号 NZ338098(A) 申请公布日期 2001.06.29
申请号 NZ19990338098 申请日期 1999.09.29
申请人 TAIT ELECTRONICS LIMITED 发明人 MANN, STEPHEN IAN
分类号 H03L7/23;(IPC1-7):H03L7/087;H03L7/18 主分类号 H03L7/23
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