| 摘要 |
PROBLEM TO BE SOLVED: To simplify clock signal wiring in the shortest distance, and to stably and surely operate even a clock signal with high frequencies, and to reduce manufacturing costs. SOLUTION: A logic chip 7 formed in a multi-chip module is provided with a clock output terminal CKOT for outputting a clock signal. This clock output terminal CKOT is formed at the central part of the logic chip 7, and clock signal wiring CKIO is connected with each of clock signal input terminals CKIN of memories 3-6 arranged near the peripheral part with the clock signal output terminal CKOT as a center. The clock output terminal CKOT is formed at the central part of the logic chip 7, so that the clock signal wiring CKIO connecting the clock output terminal CKOT with the clock signal input terminals CKIN can be easily and linearly wired in the shortest distance, and that the semiconductor device can be stably operated. |
