| 摘要 |
PROBLEM TO BE SOLVED: To realize a vector normalization arithmetic unit capable of performing a high speed arithmetic operation with a simple configuration. SOLUTION: The vector normalization arithmetic unit 30 is provided with a divider 32 for dividing each component of a vector applied in a floating decimal point type into a code part, exponent part, and mantissa part, an adder 33 for adding spore bits to the most significant bit of the mantissa part, a memory 36 for storing the normalization arithmetic result of the vector, whose component is respectively provided with a preliminarily decided prescribed value, a comparator 34 for comparing the size of the exponent part of each component, an address decoder 35 for shifting the decimal point position of the exponent part, so that the value of the exponent of each component of the vector can be made the same, based on the compared result of the size of the exponent part, and for generating an address on the memory, in which the normalization arithmetic result of the vector corresponding to the value defined with the bits of the exponent part, and a code matching circuit 37 for conducting code matching with the arithmetic result read from the memory by referring to the code part. |
