发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL circuit that can always normally be started independently of a characteristic of a device and a characteristic of a component to be connected to the outside. SOLUTION: In this PLL circuit whose VCO 10 is connected to the outside of the device, the device is provided with a register 24 that stores an N value to designate a frequency division ratio, a programmable divider 21 that applies frequency division to a signal from the VCO at a frequency division ratio in response to the N value from this register, a reference signal generator 25 that generates a reference signal fREF, and control circuits 22, 23, 40 that generate and outputs a control signal to decide the oscillated frequency of the VCO on the basis of a feedback signal fFB from the programmable divider and the reference signal fREF. A processing section 30 stops update of the N value stored in the register for a prescribed time after application of power, allows the control circuits to stop generation of the control signal, starts updating the N value stored in the register after the lapse of a prescribed time, and allows the control circuits to start generation of the control signal.
申请公布号 JP2001177403(A) 申请公布日期 2001.06.29
申请号 JP19990359916 申请日期 1999.12.17
申请人 NEC CORP 发明人 OSHIRO TSUKASA
分类号 H03L7/10;H03L7/08;H03L7/18;H03L7/183;H03L7/199;H04B1/26 主分类号 H03L7/10
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