发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To limit the frequency of an oscillated output from a PLL circuit having same dispersion within a prescribed range of an upper limit frequency and a lower limit frequency. SOLUTION: A horizontal period measurement section 5 uses a horizontal period measurement clock signal Sm, to measure the period of a horizontal synchronizing signal Sh as a reference signal and provides an output of a measured value A. A frequency division ratio calculation section 6 calculates the oscillation frequency of a voltage controlled oscillator 4, calculates a frequency division ratio set to the upper limit frequency and calculates a frequency division ratio set to the lower limit frequency according to a prescribed calculation equation on the basis of a preset upper limit frequency, lower limit frequency and the measured data. A frequency division ratio calculation section 6 sets a frequency division ratio set to a frequency divider 1, so that the oscillation frequency of the voltage controlled oscillator 1 that is calculated in the above will not exceed the upper limit frequency or the lower limit frequency.
申请公布号 JP2001177394(A) 申请公布日期 2001.06.29
申请号 JP19990360772 申请日期 1999.12.20
申请人 FUJITSU GENERAL LTD 发明人 ISHII HIROBUMI
分类号 H04N5/46;H03L7/08 主分类号 H04N5/46
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