发明名称 MEMORY CONTROL CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a memory control circuit for efficiently verifying an LSI, on which a memory is loaded by quickly initializing the memory. SOLUTION: A ring oscillator 10 generates a high-speed clock signal in a reset signal period. A counter 20 inputs the high-speed clock signal, and generates initial value write address of a memory 60. A writing address signal selecting circuit 40 inputs the initial value writing address signal generated by the counter and a data write address signal in a normal operating state, and selects the initial value write address signal according to a reset signal, and inputs it to a memory. A write control signal selecting circuit 50 inputs the high-speed clock signal and a wiring control signal in a normal operating state, and selects the high-speed clock signal according to the reset signal, and outputs it to the memory. A write data selecting circuit 30 inputs the prescribed initial value data and a memory wiring data in the normal operating state, and selects the initial value data according to the reset signal, and outputs it to the memory.</p>
申请公布号 JP2001175496(A) 申请公布日期 2001.06.29
申请号 JP19990357647 申请日期 1999.12.16
申请人 NEC SHIZUOKA LTD 发明人 TANAKA TAKASHI
分类号 G01R31/28;G06F1/24;G06F11/22;G06F12/16 主分类号 G01R31/28
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