| 摘要 |
PROBLEM TO BE SOLVED: To provide a dielectric stack compatible with chemical and mechanical polishing process, without forming gaps, joints and divots. SOLUTION: A method for manufacturing an integrated circuit device forms an interlevel dielectrics (ILD) 212, 312, using high density plasma caplayers(HDP) 208, 308. A liner layer 104 and an HSQ layer 106 are deposited in a metal wire 102 on a semiconductor body 100, followed by deposition of PETEOS layers 210, 310 on the HSQ layer 106. Gaps, joints or divots may be formed in the HSQ layer 106. Then HDP cap layers 208, 308 are deposited by means of high deposition ration to etching. The HDP processing forces to open any gaps, joints or dibots to have them filed by the HDP materials 208, 308. A structure formed through the method is subjected to chemical and mechanical polishing process after/before the HDP processing.
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