发明名称 LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent deterioration in electric characteristics and to decrease non-wiring by giving priority to short wiring concerning a layout method for semiconductor integrated circuit, for which a computer is used. SOLUTION: This method has a first step for finding the length of a wiring route between terminals to be wired, a second step for finding a clearance between these terminals, and a third step for comparing the clearance with the length of the wiring route and adopting that wiring route when the length of the wiring route is shorter than a certain constant multiple of the clearance. By performing wiring according to the adopted wiring route, priority in wiring is given to short wiring and detour wiring is decreased. Besides, when all the wiring is not completed, all the wiring is performed by repeating operation while increasing a certain constant for determining the relation of the clearance and the wiring route length step by step.
申请公布号 JP2001176972(A) 申请公布日期 2001.06.29
申请号 JP19990357250 申请日期 1999.12.16
申请人 MATSUSHITA ELECTRONICS INDUSTRY CORP 发明人 MISHIMA HIDEKI
分类号 H01L21/82;G06F17/50;(IPC1-7):H01L21/82 主分类号 H01L21/82
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