| 摘要 |
In a method for verifying a timing at an object logic cell between a first signal and a second signal in a logic circuit with a plurality of logic cells including the object logic cell, there are determined first delay data of the first signal from a first external input terminal to the object logic cell, first waveform slew data of the first signal to the object logic cell and first signal data indicating a frequency, duty ratio and jitter of the first signal and a second waveform slew data of the second signal to the object logic cell. A first portion of a first waveform of the first signal at the object logic cell is calculated in time based on the first delay data, and the first waveform slew data and the first signal data a second portion of a second waveform of the second signal at the object logic cell is calculated in time based on the second waveform slew data. Then, it is determined whether the first portion of the first waveform overlaps the second portion of the second waveform.
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