| 摘要 |
Design-based reticle inspection allows for a more efficient prioritization than typical human labor intensive reticle inspection techniques. A processed netlist for an integrated circuit (IC) and/or layout of the IC is used to determine the relative priorities of reticle defects identified by a reticle inspection device. In one embodiment, the processed netlist is a netlist that is derived by a verification tool based on a layout of the IC design. The processed netlist can include component coordinates that indicate the position of the components of the IC. In one embodiment, the processed layout includes derived geometry, for example, critical dimensions and/or device identifications that can be used to determine regions of interest. In one embodiment, defects are prioritized based on the location of the defects with respect to functional portions of the integrated circuit. For example, regions of interest can be determined around certain IC structures (e.g., transistor gates, minimum dimension lines, line corners). In one embodiment, defects within the regions of interest can be repaires while defects outside of the care zone can be ignored. More complex defect prioritization can be provided by prioritizing defects, for example, by size within the regions of interest. By prioritizing defects by areas of interest, the number of defects analyzed by a human operator and/or simulator can be decreased thereby decreasing the cost of reticle inspection and repair.
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