发明名称 |
METHOD OF OPERATING ON A NET-LIST DESCRIBING AN INTEGRATED CIRCUIT DESIGN, METHOD OF GENERATING TEST VECTORS TO PROVIDE REDUCED NUMBERS OF MISCOMPARES BETWEEN MEASURED TEST RESULTS FROM A PROTOTYPE INTEGRATED CIRCUIT DESIGN AND SIMULATED PERFORMANCE |
摘要 |
A method of operating on a net-list describing an integrated circuit design for use with an automated test pattern generator for testing an integrated circuit built using the design is described. The method includes replacing a defective portion of the design in test mode with a substitute circuit to reduce testing impact of the defective portion. The method includes identifying a first defective portion of the integrated circuit design in the net-list, determining conditions under which the first defective portion is likely to malfunction and replacing the first defective portion in the net-list with another first portion that provides unknown output signals representing an unknown state in response to conditions under which the first defective portion is likely to malfunction.
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申请公布号 |
WO0145565(A2) |
申请公布日期 |
2001.06.28 |
申请号 |
WO2000US42680 |
申请日期 |
2000.12.07 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS NV;PHILIPS SEMICONDUCTORS, INC. |
发明人 |
HAYEM, FREDERIC;ARNOULD, PATRICK |
分类号 |
G06F17/50;G01R31/3183;H01L21/82;(IPC1-7):A61B8/00 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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