发明名称 |
Configuration for testing a multiplicity of semiconductor chips |
摘要 |
The configuration allows for testing a multiplicity of semiconductor chips with respect to critical parameters on the wafer level. Each of the semiconductor chips on a semiconductor wafer is additionally provided with at least one option pad. The option pad allows access for a test program to the chip for separating out the semiconductor chips which do not correspond to predetermined requirements for critical parameters. |
申请公布号 |
US2001005144(A1) |
申请公布日期 |
2001.06.28 |
申请号 |
US20000748531 |
申请日期 |
2000.12.26 |
申请人 |
FEURLE ROBERT;SAVIGNAC DOMINIQUE |
发明人 |
FEURLE ROBERT;SAVIGNAC DOMINIQUE |
分类号 |
G01R31/28;G01R31/3185;G11C11/401;G11C29/56;H01L21/66;(IPC1-7):G01R31/26 |
主分类号 |
G01R31/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|