发明名称 |
Memory device with reduced power consumption when byte-unit accessed |
摘要 |
A memory device is arranged in such a manner that an access-target memory cell is selected from a plurality of memory cells in accordance with the level of the byte-enable signal at the timing when the level of the corresponding row address strobe signal (/RAS signal) changes, and by this arrangement, the problem resided in the conventional memory device that it could not be decided as to whether a memory block in the DRAM core was to be a selected or non-selected byte until the fall of the corresponding column address strobe signal (/CAS signal), and thus the column decoder and the preamplifier that start operating at the fall of the /RAS signal could not be efficiently controlled is solved, and due to this, electric power that might otherwise be consumed at the time of executing a byte-unit access to the wide-bus DRAM can be reduced.
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申请公布号 |
US6252807(B1) |
申请公布日期 |
2001.06.26 |
申请号 |
US19990457529 |
申请日期 |
1999.12.09 |
申请人 |
MITSUBISHI ELECTRIC ENGINEERING COMPANY, LIMITED;MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
SUZUKI TOMOAKI;SONPACHI HARUKO |
分类号 |
G11C11/407;G11C8/18;G11C11/401;G11C11/4076;G11C11/408;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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