发明名称 Virtual cache registers with selectable width for accommodating different precision data formats
摘要 A structure and method for processing data comprises a processing unit having a base cache, base registers having a base width and being operatively connected to the processing unit, and virtual cache registers having a virtual width and being located in the base cache and operatively connected to the processing unit, wherein a base processing precision of the processing system is determined by the base width of the base registers and a selectable enhanced processing precision is determined by the virtual width of the virtual cache registers, wherein the base registers store base instructions and data and the virtual cache registers store enhanced data, the virtual width being greater than the base width, and wherein the base cache includes tags identifying a portion of the base cache as the virtual registers, the virtual cache registers being accessible by the processing unit only for execution of enhanced instructions for providing the enhanced processing precision.
申请公布号 US6253299(B1) 申请公布日期 2001.06.26
申请号 US19990224793 申请日期 1999.01.04
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 SMITH JACK R.;VENTRONE SEBASTIAN T.;WILLIAMS KEITH R.
分类号 G06F9/30;G06F9/318;G06F12/08;(IPC1-7):G06F12/00 主分类号 G06F9/30
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