| 摘要 |
A method and a tool for quickly evaluating the circuit response of VLSI designs in the presence of parasitics assists in improving VLSI designs. Offending induced voltgages are quickly identified through a simple approximation procedure, and the circuit lines where such voltages are induced are marked for evaluation with tools that make an accurate assessment. When it is determined that these circuit lines do exceed predetermined thresholds, the circuit designer is alerted to the need to redesign the circuit or its layout. The tool disclosed considers each circuit line of the VLSI circuit, and with respect to each considered circuit line, computes an estimated peak voltage due to the parasitics. The computations are very simple, involving only a summation of terms, each of which involves a quotient of one RC product by a sum of two RC products.
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