| 摘要 |
A CMOS-based circuit for translating a differential-input into a single-ended output capable of driving large loads with little or no compromise in speed. This translator provides a symmetric single-ended output signal capable of driving a wide range of loads with minimal distortion. In contrast to earlier such translators, the circuit of the present invention ensures that the output signal is coupled directly to the high-voltage rail after being switched to logic HIGH and that that coupling remains in effect until an input signal causing the output to switch to logic LOW is received. Similarly, when the output signal is switched to logic LOW, it is coupled directly to the low-voltage rail of the circuit and left so coupled until it is affirmatively switched to logic HIGH. This feature ensures that regardless of load, the output signal completely switches to the proper logic stage.
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