Method for analyzing circuit delays caused by capacitive coupling in digital circuits

摘要

A method for designing and fabricating an integrated circuit is described. An increase or a decrease in a total propagation delay time 311 of a signal on a victim net 203 is accurately modeled using a modified decoupled simulation model 300. Victim net 203 is modeled as a distributed capacitor 320a-c that has a total value equal to Cgnd+2*K*Ccoup. A match propagation delay time which includes a variation in propagation delay caused by signal coupling from aggressor nets located adjacent to the victim net is determined by simulating a representative circuit using a coupled distributed load simulation model to accurately determine the match propagation delay time. K is determined using an equation in which K=1+(match delay-unmodified delay)/(2*R*Ccoup). R is the effective drive resistance of a buffer which drives the victim net and associated signal trace resistance.