| 摘要 |
A semiconductor memory device having a row redundancy scheme in which the time to enable a word line during a normal path is less than that of a conventional device, to enhance the operation speed of a memory chip, and the number of common redundancies are maximized to enhance the redundancy capability, and a method for curing a defective cell. The semiconductor memory device has a plurality of global blocks, each of which includes a plurality of unit matrixes having a normal block and a redundancy block, a normal division word line driver, a redundancy division word line driver, a main decoder and an auxiliary decoder. In the main decoder, an output signal is selectively activated according to a row address signal regardless of using the redundancy cell. Also, in the auxiliary decoder, when a corresponding global block is selected according to the row address signal for selecting a global block in a normal operation mode or a redundancy scheme of the corresponding block is used in the redundancy operation mode, an output signal is selectively activated according to the row address signal.
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