MULTI-BIT SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: A multi-bit sense amplifier of semiconductor memory device is provided to improve an operation speed by comparing data from a memory cell at the same time via a plurality of sense amplifiers having different reference levels from each other. CONSTITUTION: Sense amplifiers(S/A1-S/A3) are supplied with data of a level from a memory cell(MC), which stores an electric signal having one of four different levels(A-D). The sense amplifier(S/A1) has a reference level(AB) of an intermediate value between a signal level(A) for determining a logic value of data and a signal level(B). The sense amplifier(S/A1) outputs a logic value "0" when an input data level of the sense amplifier(S/A1) is lower than the reference level(AB) and a logic value "1" when an input data level of the sense amplifier(S/A1) is higher than the reference level(AB). The sense amplifier(S/A2) has a reference level(BC) of an intermediate value between a signal level(B) for determining a logic value of data and a signal level(C). The sense amplifier(S/A2) outputs a logic value "0" when an input data level of the sense amplifier(S/A2) is lower than the reference level(BC) and a logic value "1" when an input data level of the sense amplifier(S/A2) is higher than the reference level(BC). The sense amplifier(S/A3) has a reference level(CD) of an intermediate value between a signal level(C) for determining a logic value of data and a signal level(D). The sense amplifier(S/A3) outputs a logic value "0" when an input data level of the sense amplifier(S/A3) is lower than the reference level(CD) and a logic value "1" when an input data level of the sense amplifier(S/A3) is higher than the reference level(CD).