| 摘要 |
PURPOSE: To provide an address control circuit in which expansion of the circuit scale is prevented and the circuit delay time is less when an IC memory operated at a high speed is tested in a semiconductor test device. CONSTITUTION: In the semiconductor test device 1, a sequence control section 10 converts an input signal from a tester control CPU into address scramble data and an address clock signal. An address selection control section 20 stores address scramble data based on an address clock signals. The address selection control section 20 outputs address scramble data, that is, an address selecting signal to a 32TO1 selector section 30, and the 32TO1 selector 30 converts an address of a memory IC to an one-dimensional address. Therefore, an address of a memory IC can be directly made in one-dimension, at the time of testing a high speed memory IC, the circuit delay and expansion of circuit scale can be prevented.
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