| 摘要 |
PURPOSE: A semiconductor device with tapered gate and process for fabricating the device is provided to shorten its length less than 50 nm, and the device gate is bounded by spacers that define the gate length of the device. CONSTITUTION: Gates(140,141,145) of the MOS device is bounded by spacers(135), which are in turn bounded by a trench in a trench dielectric layer(130) formed on a semiconductor substrate(100). The device is formed by lithographically defining a sacrificial gate on the surface of the semiconductor substrate. The trench dielectric layer(130) is then formed on the semiconductor substrate and adjacent to the sacrificial gate. The trench dielectric layer is planarized and, subsequent to planarization, the sacrificial gate is no longer covered by the trench dielectric layer. The sacrificial gate is then removed, which leaves a trench in the trench dielectric layer. Dielectric spacers(135) are then formed in the trench. The distance between the spacers defines the gate length of the semiconductor device. After the spacers are formed, the device gates(140,141,145) are formed. At least a portion of the gate is formed in the trench.
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