发明名称 EVENT TESTER ARCHITECTURE FOR MIXED SIGNAL INTEGRATED CIRCUIT
摘要 PURPOSE: The event tester architecture for mixed signal integrated circuit is provided to test a mixed signal device by including test modules which have different capabilities, so testing a digital and analog function simultaneously. CONSTITUTION: This semiconductor test system includes a tester module having two or more different types of performances, a test head having two or more types of test modules having analog and digital types of performances combined by two or more pieces with each other and mounted thereto, a means for electrically connecting the test module to a tested device, an additional circuit provided between the test module and tested device according to the analog function block and the digital function block of the tested device, and a host computer controls the operation of the entire system by communicating with the test module mounted on the test head through a system bus.
申请公布号 KR20010051609(A) 申请公布日期 2001.06.25
申请号 KR20000066750 申请日期 2000.11.10
申请人 ADVANTEST CORPORATION 发明人 SUGAMORI SHIGERU
分类号 G01R31/316;G01R31/28;G01R31/3167;(IPC1-7):G01R31/26 主分类号 G01R31/316
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