| 摘要 |
PURPOSE: A linear capacitor structure in a CMOS process is provided to achieve a good linear characteristic which can be integrated in CMOS. CONSTITUTION: In a set of four capacitors coupled in parallel between a first terminal(610) and a second terminal(614), the first capacitor(601) is composed of an n-type polysilicon-made top electrode plate(611) coupled with the first terminal(610), a bottom electrode(612) which is coupled with the second terminal(614) and composed of a first accumulation/reduced region such as n-well region, and a first dielectric region between the top electrode plate(611) and the bottom electrode plate(612). The second capacitor(602) has the same structure, including an n-polysilicon top electrode plate(621), an n-well bottom electrode plate(622), etc., except the coupling with opposite lines to the first capacitor(601). The other third and fourth capacitors(603, 604) have the same constitution, except the constitution with p-type polysilicon top electrode plates(631, 641).
|
