MICROPROCESSOR FOR UTILIZING IMPROVED BRANCH CONTROL INSTRUCTION, BRANCH TARGET INSTRUCTION MEMORY, INSTRUCTION LOAD CONTROL CIRCUIT, METHOD FOR MAINTAINING INSTRUCTION SUPPLY TO PIPE LINE, BRANCH CONTROL MEMORY AND PROCESSOR

摘要

PURPOSE: To shorten and/or remove access latency, and to reduce the code size, and to increase the executing speed by applying a strong and elastic improved branch operation instruction format implemented by a pipe line processor. CONSTITUTION: In this improved branch control instruction for optimizing the performance of a program to be executed by a processor and the processor using a branch instruction, it is possible to implement various new branch control instructions which are most suitable for a certain specific arithmetic environment by an elastic instruction parameter field. The instructions are provided with different predictive bits so that the load of a target institution to a buffer can be optimized before the execution of the program. Therefore, a pipe line in a processor can exhibit excellent performance at the time of executing the actual program.