发明名称 PROCESSOR SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a processor system suitable for processing a communication protocol and capable of executing a generated processing step, especially, a data shift arithmetic operation at relatively small costs, that is, in the minimum number of execution cycles and with the minimum capability consumption. SOLUTION: A data shift instruction is defined as an instruction to set the number of data units to be shifted in the configuration of data blocks to a processor unit under the data shift instruction, and the processor unit depending on the data shift instruction is constituted so that the data units in the number equivalent to the number set by the data shift instruction can be shifted between a data memory and an intermediate memory unit.
申请公布号 JP2001166918(A) 申请公布日期 2001.06.22
申请号 JP20000305390 申请日期 2000.10.04
申请人 INFINEON TECHNOLOGIES AG 发明人 NIE XIAONING
分类号 G06F7/00;G06F9/308;G06F9/312;G06F9/315;G06F12/04;G06F13/00 主分类号 G06F7/00
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