发明名称 |
METHOD AND APPARATUS FOR REDUCING TRANSISTOR AMPLIFIER HYSTERESIS |
摘要 |
The present invention provides a biasing method and apparatus which provides bias circuits of radio frequency (RF) power transistors with a low reactive impedance at low frequencies to reduce hysteresis related distortio n without affecting the transistor input or output impedance or any impedance matching network which may be used. In one embodiment, the invention is incorporated in a lateral diffused metal-oxide semiconductor (LDMOS) transistor to reduce hysteresis brought about by a drain bias circuit withou t any impact on the transistor output impedance. By removing the effect of the bias circuit at RF frequencies, the bias circuit can be designed with a low reactive impedance at low frequencies without any material consequences on the transistor output impedance. With a low enough reactive impedance, the hysteresis introduced by the bias circuit is substantially reduced. An auxiliary bias feed external to an RF transistor package is also embodied.
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申请公布号 |
CA2327887(A1) |
申请公布日期 |
2001.06.22 |
申请号 |
CA20002327887 |
申请日期 |
2000.12.07 |
申请人 |
NORTEL NETWORKS CORPORATION |
发明人 |
ILOWSKI, JOHN J.;GRUNDLINGH, JOHAN M.;LEROUX, ROBERT;SMILEY, RUSSELL C. |
分类号 |
H03F1/32;(IPC1-7):H03F1/32 |
主分类号 |
H03F1/32 |
代理机构 |
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地址 |
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