| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a start-stop data interface circuit that can cope with the even with decreased period of data transfer and realize high-speed serial data reception. SOLUTION: This start-stop data interface circuit has F/F 12-14 that receive a plurality of transmission data in parallel, delay elements 30, 31 that give a clock to each clock terminal of each F/F with a phase difference, and a clock generator 15 that uses outputs D1-D3 of each F/F and a delayed clock by the delay elements 30, 31 to generate a sampling clock CLK. Even if one of the CLK1-3 competes with data DATA, since the clock generator 15 can control a start signal, the start-stop data interface circuit can serially receive the transmission data DATA with the stable CLK.</p> |
