发明名称 METHOD FOR ANALYZING SHORT CIRCUIT FAILURE
摘要 PROBLEM TO BE SOLVED: To provide an analyzing method for a short circuit failure capable of analyzing the failure even in a large scale integral circuit having several million gates and more, and analyzing it at a high speed. SOLUTION: Plural measurement patterns used for a stationary power supply current test of an integral circuit by changing the setting of a logical state in the integral circuit are made, an internal state value 0/1 for every net at the time when the measurement pattern is applied is led out by the simulation of the integral circuit, and a normal or abnormal test result is obtained for every measurement pattern by the stationary power supply current test applying the plural measurement patterns to the integral circuit determined to be a defective device. Based on these measurement patterns, internal state values, and test results, a state value variable storing the internal state values of all measurement patterns for every net and a test result variable storing the normal or abnormal test result for every measurement pattern are produced, and a combination of the state value variable for every net and the test result variable are compared between the nets to determine a short circuit failure spot in the integral circuit.
申请公布号 JP2001166001(A) 申请公布日期 2001.06.22
申请号 JP19990345739 申请日期 1999.12.06
申请人 FUJITSU LTD 发明人 NISHIDE KENZO
分类号 G01R31/28;G01R31/02;G01R31/26;G01R31/30;G01R31/3183;(IPC1-7):G01R31/28 主分类号 G01R31/28
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