| 摘要 |
PROBLEM TO BE SOLVED: To provide a device capable of reducing the delay time of instruction processing. SOLUTION: The prefetch of an instruction is operated by an instruction fetch controlling part 9 for outputting an instruction fetch instruction to an instruction cache 2. The instruction fetch controlling part 9 is provided with a fetch address generating part 9-1, a branch history 9-2, and a priority deciding circuit 9-3. The priority deciding circuit 9-3 decides whether an instruction fetch request should be issued or an instruction prefetch request should be issued. At the time of operating the instruction prefetch, the calculation of the prefetch address is operated by the fetch address generating part 9-1. The priority deciding circuit 9-3 decides the priority of the instruction fetch or instruction prefetch or re-instruction fetch instructions or the like, and transmits the request to the instruction cache 2. Also, the proper address among the plural inputted addresses is selected and outputted by a selector 9-4 controlled by the priority deciding circuit 9-3.
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