| 摘要 |
PROBLEM TO BE SOLVED: To provide a method and a device for evaluating the performance of a multiprocessor while considering memory fetch and data access. SOLUTION: Storage means 2-1 to 2-n preserve instruction fetch information composed of an issue interval between instruction fetch timing, which is sampled by trace driven simulators 1-1 to 1-n corresponding to respective element processors, on the assumption of complete hit of an instruction cache and issue timing of a preceding instruction, which occupies an instruction buffer entry to store a fetched instruction, and a fetch address. On the basis of the instruction fetch information, CPU simulators 4-1 to 4-n estimate an instruction fetch cycle. An event processing part 5 processes events from the CPU simulators 4-1 to 4-n and an event from a memory system simulator 6 and simulates a multiprocessor system. |
