发明名称 MEMORY SUBSYSTEM AND MEMORY CONTROL UNIT
摘要 PROBLEM TO BE SOLVED: To improve the performance of a memory control unit, especially, to provide a high performance for effectively utilizing high-speed data transfer, that a fiber channel has, and to enable the connection of a host computer having plural kinds of interfaces. SOLUTION: A loop 133 is a common loop transmission line having a fiber channel interface. HIFC 103, 104 and 105 are respectively connected with host computers 100, 101 and 102 of different interfaces and have a function for conversion with the fiber channel interface as needed. Each of control processors 114-117 is a processor shared by the HIFC 103-105. Each of control processors 114-117 refers to FCAL managing information, fetches a frame having a set address among frames flowing on the loop 133 and processes the input/output request within the set LUN range.
申请公布号 JP2001167040(A) 申请公布日期 2001.06.22
申请号 JP19990353806 申请日期 1999.12.14
申请人 HITACHI LTD 发明人 NAKAYAMA SHINICHI;YOKOHATA SHIZUO
分类号 G06F13/10;G06F3/06;G06F11/20;G06F13/38;(IPC1-7):G06F13/10 主分类号 G06F13/10
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