发明名称 |
STATIC RANDOM ACCESS MEMORY |
摘要 |
PROBLEM TO BE SOLVED: To provide a static RAM(random access memory) where the data can be stably read out even with its slow operation and also the increase of its circuit scale can be satisfactorily suppressed. SOLUTION: This static RAM includes a memory cell and a data line pre- charge circuit 106 which are placed between a positive data line D and a negative data line DB. Two PMOS 107 and 108 are connected in series between both lines D and DB and the power voltage Vcc is applied to a connecting point between both PMOS 107 and 108. Then the gate of the PMOS 107 whose drain or source is connected to the line D is connected to the line DB, and the gate of the PMOS 108 whose source or drain is connected to the line DB is connected to the line D. In such a constitution, the potential of the data D or DB is clamped by the voltage Vcc in a low impedance state according to the stored data when the data are read out of a memory. Thus, the potential of the read-out data is stabilized.
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申请公布号 |
JP2001167583(A) |
申请公布日期 |
2001.06.22 |
申请号 |
JP19990349154 |
申请日期 |
1999.12.08 |
申请人 |
HITACHI LTD;HITACHI ENG CO LTD |
发明人 |
OGAWA HIROAKI;HASHIMOTO SHIGEYUKI;KONO JUNICHI |
分类号 |
G11C11/419;(IPC1-7):G11C11/419 |
主分类号 |
G11C11/419 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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