| 摘要 |
An impedance matched LDMOS power transistor package (20) includes a conductive flange (22) serving as a combined heat spreader, mounting mechanism and relative ground, with a dielectric window substrate (24) attached to, and exposing a portion of, the flange. A silicon die (32) is attached to the exposed portion of the flange within the window substrate, the die having a plurality of electrodes (34) formed thereon, the electrodes each having respective input (gate) (36) and output (drain) (38) terminals, the ground terminals (40) electrically coupled to the flange. An input lead (42) is attached to the window substrate, electrically isolated from the flange, the input lead electrically coupled to the electrode input terminals (36) via an input transmission path. The input transmission path includes an input matching capacitor (52) having a first terminal (50) electrically coupled to the input lead, a second terminal (56) electrically coupled to the electrode input terminals, and a ground terminal (68). The first and second capacitor terminals are separated from the ground terminal by a dielectric layer (70), with the first capacitor terminal electrically coupled to the second capacitor terminal by a resistive path (72), the resistive path forming a common gate resistor along the input transmission path. |
