发明名称 Method, circuit and/or architecture for reducing gate oxide stress in low-voltage regulated devices
摘要 An apparatus comprising a first circuit, a second circuit and a switch. The first circuit may be configured to receive a first supply voltage and may be coupled to a first ground. The second circuit may be configured to receive a second supply voltage and may be coupled to a second ground. The second circuit may be disabled in response to a control signal. The first and second supply voltages may be controlled by a reference voltage. The switch may be coupled between the first and second circuits and may be configured to connect the first and second circuits when the second circuit is disabled.
申请公布号 US6249177(B1) 申请公布日期 2001.06.19
申请号 US20000672396 申请日期 2000.09.28
申请人 CYPRESS SEMICONDUCTOR CORP. 发明人 SAVAGE DERRICK J.;SARIPELLA SATISH C.
分类号 G05F3/02;(IPC1-7):G05F3/02 主分类号 G05F3/02
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