发明名称 Semiconductor memory device with a stacked capacitance structure
摘要 A semiconductor memory device including memory cells with the stacked-capacitor structure that makes it possible to prevent a contact pad from being damaged. This device includes a memory cell area and a peripheral circuit area formed on a semiconductor substrate. An interlayer insulating layer having first and second penetrating holes is formed to cover the entire substrate. A capacitor has lower and upper electrode and a dielectric located between these electrodes. The lower electrode is electrically connected to the first element through the first penetrating hole. Each of the peripheral circuits has a second element, a contact pad electrically connected to the second element, a pad insulating layer formed to cover the contact pad, a pad protection layer formed on the pad insulating layer, and an interconnection conductor electrically connected to the contact pad through a contact hole penetrating the pad protection and pad insulating layers. The contact pad is electrically connected to the second element through the second penetrating hole. The lower electrode and the contact pad are made by using a same conductive layer. The dielectric and the pad insulating layer are made by using a same insulative layer. The upper electrode and the pad protection layer are made by using a same conductive layer.
申请公布号 US6249054(B1) 申请公布日期 2001.06.19
申请号 US19980110888 申请日期 1998.07.07
申请人 NEC CORPORATION 发明人 TANIGAWA TAKAHO
分类号 H01L21/768;H01L21/8242;H01L23/522;H01L27/108;(IPC1-7):H01L23/48 主分类号 H01L21/768
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