发明名称 Digital frequency phase locked loop (FPLL) for vestigial sideband (VSB) modulation transmission system
摘要 In a digital frequency phase locked loop (FPLL) for a grand alliance (GA) HDTV receiver using a vestigial sideband (VSB) modulation transmission system, the digital FPLL for a VSB transmission system having a VCO and a plurality of NTSC carrier eliminating filters for eliminating interference of NTSC adjacent channels includes a filter for eliminating high-frequency components by converting a digital signal output from one of the plurality of NTSC carrier eliminating filters, a delay for delaying the high-frequency-component-eliminated signal by a predetermined width so that its frequency-versus-phase characteristics are changed linearly, symbol inverter for inverting the symbol of the digital signal output from another of the plurality of NTSC-carrier eliminating filters, a switch for selectively outputting the symbol-inverted signal and the digital signal output from another filter, a second filter for limiting the selectively output signal to a predetermined frequency band, a digital-to-analog (D/A) converter for converting the band-limited-digital signal into an analog signal. The result is that the frequency-versus-phase characteristics of the filter is linear, and the size of digital ASICs gates are remarkably reduced.
申请公布号 US6249559(B1) 申请公布日期 2001.06.19
申请号 US19960702094 申请日期 1996.08.23
申请人 L.G. ELECTRONICS INC. 发明人 JUN JUNG-SIG
分类号 H03C1/60;H04L27/00;H04L27/02;H04N5/21;H04N5/44;(IPC1-7):H03D3/24;H03D3/00;H04L27/22;H04N5/455 主分类号 H03C1/60
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