| 摘要 |
A full signal swing differential output path circuit for rapidly transferring a latched data value on a pair of complementary global data nodes (QT and QB) to a single-ended output of a compilable memory instance. At least one tri-statable sense amplifier is disposed between the complementary global data nodes which operates to sense a small differential voltage between a pair of complementary bitlines disposed in a bank of memory storage cells during an access operation associated therewith. A pair of precharge pull up devices are provided for precharging the complementary global data nodes QT and QB to a predetermined voltage, e.g., VDD. In a preferred embodiment, the precharge pull up devices preferably comprise P-channel MOS (PMOS) devices and are actuatable by an active low precharge signal. A first output of the sense amp is coupled to one of the complementary global data nodes (QB) and the complementary output (i.e., second output) of the sense amp is coupled to the other complementary global data node (QT) to quickly drive either QT or QB to ground as soon as the bitline polarity is sensed by the sense amp. The output structure then quickly takes the full differential value between QT and QB and drives the single-ended output of the memory instance rapidly to either VDD or ground. A CMOS pass gate actuatable by an output enable signal is disposed on the QB data path, wherein the pass gate operates to drive an output pull up device coupled to the output of the memory instance. A NOR gate is coupled to the QT data path and an inverted signal derived from the output enable signal, wherein the NOR gate operates to drive a output pull down device coupled to the single-ended output of the memory instance.
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