| 摘要 |
A method of forming a test configuration for an integrated circuit employing a controlled, collapse chip connection technology to attach to another substrate is disclosed. The method includes the steps of forming one or more vias in a semiconductor substrate corresponding to the integrated circuit and forming circuitry on a top surface of the semiconductor substrate. The method further includes filling the one or more vias with a conductive material to form conductive channels through the semiconductor substrate which selectively couples to the circuitry to provide control signals thereto and receive output signals therefrom. One or more bond pads are formed on a bottom surface of the semiconductor substrate and correspond to the one or more conductive channels. The one or more bond pads on the bottom surface of the semiconductor substrate are coupled to bond pads on the another substrate using the controlled, collapse chip connection technique, which allows the top surface of the semiconductor substrate to be accessible for design verification or circuit test processes. The present invention further includes a controlled, collapse connection chip carrier system which includes a base substrate having one or more bond pads formed thereon and a circuit substrate having circuitry on a top surface thereof and one or more bonds pads on a bottom surface thereof which correspond generally to the one or more bond pads on the base substrate. The circuit substrate further includes one or more conductive channels extending therethrough which electrically couple selective portions of the circuitry on the top surface to the one or more bond pads on the bottom surface. The system further includes a controlled, collapse connection between the one or more bond pads on the base substrate and the one or more bond pads on the bottom surface of the circuit substrate which provides an electrical connection between the base substrate and selective portions of the circuitry on the top surface of the circuit substrate.
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