| 摘要 |
A data storage system having a plurality of addressable memories for storing a global variable. Each one of a plurality of controllers is adapted to request an operation on first and second data stored in the addressable memories. Each one of the addressable memories includes: a control logic for receiving the operation request and addresses of the first and second data from one of the controllers; a random access memory; and a buffer memory coupled between the bus and a random access memory. The buffer memory has a write buffer memory adapted to store the first data in response to the control logic and a read buffer memory adapted to store the second data. The second data is read from the random access memory in response to the control logic. The buffer memory includes an operation selection section having a plurality of operation units configured to perform a different predetermined operation on the first and second data fed to a pair of input ports thereof. One input port is fed by an output of the write buffer memory and the other input port is fed by an output of the read buffer memory. The operation selection section also includes a selector, fed by outputs of the plurality of logic sections, for coupling one of the operation unit outputs to the random access memory selectively in accordance with the operation requested by the controller.
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