| 摘要 |
PURPOSE: A digital signal processing device including an interrupt pending register is provided to control an interrupt simply without a circuit for converting an interrupt signal. CONSTITUTION: A digital signal processing core(31) performs interrupt routines successively corresponded to an interrupt signal corresponded as a plurality of interrupt signals(INT0, INT1, INT2) are inputted. A plurality of interrupt pending registers(330¯332) are set responded to the corresponded interrupt signal and perform an interrupt routine corresponded in the digital signal processing core(31) and are reset successively. In detail, the interrupt signals(INT0, INT1, INT2) are inputted to the digital signal processing core(31) directly and simultaneously, and the interrupt pending registers(330¯332) are set simultaneously. After the first interrupt routine is performed in the digital signal processing core(31), the interrupt pending register(330) is reset responded to a control signal(C0) generated from the digital signal processing core(31). Because the interrupt pending register(331) is a set status, the second interrupt routine is performed in the digital signal processing core(31) responded to the INT1. After the second interrupt routine is completed, the interrupt pending register(331) is reset responded to a control signal(C1) generated from the digital signal processing core(31).
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