| 摘要 |
PURPOSE: A wall charge erase circuit in a plasma display panel(PDP) is provided to improve the contrast of the PDP by erasing the wall charge with a weak discharge in a reset period. CONSTITUTION: The circuit comprises an RLC serial circuit part performing a level translation of input voltage(Ve) lower than discharge voltage(Vf) into output voltage(Vp) higher than the discharge voltage, and a discharge circuit part to supply a discharge current to help the weak discharge in the panel. The RLC serial circuit part comprises a capacitor(C1) modelling a panel whose one side is connected to a ground power supply stage, and a switch(S1) whose one side is connected to another side of the capacitor, and a resistor(R) and an inductor(L) connected to another side of the switch. The input voltage is applied over both sides of the capacitor. The discharge circuit part comprises a capacitor(C2) whose one side is connected to the ground power supply stage and has a random capacitance, and a switch(S2) switching an output terminal of the output voltage and the capacitor(C2). The capacitance of the capacitor(C2) is determined according to a load of a display electrode applied with the output voltage. The wall charge erase circuit further comprises a reverse current blocking diode(D) to block a reverse current flowing when the output voltage is at maximum, and an output terminal capacitor(Cp) connected between the output terminal of the output voltage and the ground power supply stage. |
