| 摘要 |
PURPOSE: A duplexing apparatus of an ATM board of a control station of an IMT2000 system is provided to stably maintain a system, continuously and stably maintain a high quality service and be easily adaptable in an ATM board development by implementing duplexing of ATM boards in a control station. CONSTITUTION: Cubits(11,31) receive an ATM cell inputted through a cell bus. Multiplexers(12,32) multiplex the ATM cell received from the cubits(11,13). The first buffers(13,33) are operated according to a buffer control signal of a master/slave EPLD by a CPU and provide a path for storing the ATM cells multiplexed by the multiplexers(12,32). The second buffers(14,34) are operated according to the buffer control signal of the master/slave EPLD and provide a path for storing the ATM cell received from the cubits(11,31). The third buffers(15,35) are operated according to the buffer control signal of the master/slave EPLD and provide a path for storing the ATM cell received by the cubits(11,31) and multiplexed by the multiplexers(12,32). The first SRAMs(16,36) store the ATM cell inputted through the first buffers(13,33) and the third buffers(35,15) of the other ATM board. The second SRAMs(17,37) store the ATM cell inputted through the second buffers(14,34) and the third buffers(35,15) of the other ATM board. CPUs(18,38) output a control signal according to various control information for receiving and storing the ATM cell. The master/slave EPLDs(19,39) controls a corresponding ATM board by a mater or a slave according to a control signal outputted from the CPUs(18,38) and controls operations of the first, second, third, fourth, fifth and sixth buffers. The fourth buffers(20,40) are operated according to the buffer control signal of the master/slave EPLDs(19,39) and provide a path for storing the control information of the CPUs(18,38). The sixth buffers(22,42) are operated according to the buffer control signal of the master/slave EPLDs(19,39) by the CPUs(18,38) and provide a path for storing the control information of the CPUs(18,38). The third SRAMs(23,43) store the control information of the CPUs(18,38) inputted through the fourth buffers(20,40) and the sixth buffers(42,22) of the other ATM board. DRAMs(24,44) store the control information of the CPUs(18,38) inputted through the fifth buffers(21,41) and the sixth buffers(42,22) of the other ATM board.
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