| 摘要 |
PURPOSE: A data synchronizing circuit is provided to synchronize a clock signal to data and to assure a data setup/hold time of an output data(DO). CONSTITUTION: According to the data synchronizing circuit, an input buffer(30) receives an input data(DI), and a clock buffer(32) receives a clock(CLK). A 2-input exclusive OR(XOR1) inputs a node G and a node H which are outputs of the input buffer and the clock buffer. And, a variable delay stage(33) delays the node H by adjusting a delay time(Td3) according to an output(VCON) of a charge pump(36), and a phase delay stage(34) delays the node H by a quarter of the clock(Tclk/4). A phase detector(35) receives a node I and a node J which are outputs of the variable delay stage and the phase delay stage, and the charge pump receives a node K which is an output of the phase detector. A pulse width filter(37) delays an output node L of the exclusive OR according to the output of the charge pump. And, a 2-input exclusive OR(XOR2) receives the node I and an output node M of the pulse width filter.
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